数字集成电路：设计透视（第2版影印版)/国外大学优秀教材微电子类系列 (2008 年度畅销榜NO.742 )

本书的特点主要包括： （1）将数字集成电路设计中电路与系统的视角统一起来，在系统深入地介绍了深亚微米条件下半导体器件的知识和最基本的反相器后，作者逐渐将这些基础知识引入到更加复杂的模块，比如门、寄存器、控制器、加法器、乘法器和存储器等。在深亚微米的设计条件下，设计者不仅仅需要考虑整个系统的设计问题，还要随时警惕在电路级——比如器件和连线所带来的问题。 （2）本书是第一本将数字集成电路设计问题集中在深亚微米条件下的参考书，并且提供了一个深亚微米条件下的简晶体管模型。另外针对深亚微米条件下设计人员所面对的新挑战，例如互连线问题、信号完整性问题、时钟分布问题、功耗问题等，全书都做了非常详细的论述。（3）书中的内容紧扣当今数字集成电路设计的核心问题，并通过大量的设计实例向读者介绍了最新的设计技术和工程发展现状与趋势。

Chapterl: Introduction\r\n 1.1 A Historical Perspective\r\n 1.2 Issues in Digital Integrated Circuit Design\r\n 1.3 To Probe Further\r\n 1.4 Exercises\r\n PART 1: A CIRCUIT PERSPECTIVE\r\nChapter 2: The Devices\r\n 2.1 Introduction\r\n 2.2 The Diode\r\n 2.2.1 A First Glance at the Device\r\n 2.2.2 Static Behavior\r\n 2.2.3 Dynamic, or Transient, Behavior\r\n 2.2.4 The Actual Diode-Secondary Effects\r\n 2.2.5 The SPICE Diode Model\r\n 2.3 The MOS(FET) Transistor\r\n 2.3.1 A First Glance at the Device\r\n 2.3.2 Static Behavior\r\n 2.3.3 Dynamic Behavior\r\n 2.3.4 The Actual MOS Transistor-Secondary Effects\r\n 2.3.5 SPICE Models for the MOS Transistor\r\n 2.4 The Bipolar Transistor\r\n 2.4.1 A First Glance at the Device\r\n 2.4.2 Stalic Behavior\r\n 2.4.3 Dynamic Behavior\r\n 2.4.4 The Actual Bipolar Transistor-Secondary Effects\r\n 2.4.5 SPICE Models for the Bipolar Transistor\r\n 2.5 A Word on Process Variations\r\n 2.6 Perspective: Future Device Developments\r\n 2.7 Summary\r\n 2.8 To Probe Further\r\n 2.9 Exercises and Design Problems\r\n Appendlx A: Layout Design Rules\r\n Appendlx B: Small-Slgnal Models \r\nChapter 3: The Inverter\r\n 3.1 Introduction\r\n 3.2 Delinitions and Properties\r\n 3.2.1 Area and Complexity\r\n 3.2.2 Functionality and Robustness: The Static Behavior\r\n 3.2.3 Performance: The Dynamic Behavior\r\n 3.2.4 Power and Energy Consumption\r\n 3.3 The Static CMOS Invener\r\n 3.3.1 A First Glance\r\n 3.3.2 Evaluating the Robustness of the CMOS Inverter: The Static Behavior\r\n 3.3.3 Perfonnance of CMOS Inverter: The Dynamic Behavior\r\n 3.3.4 Power Consumption and Power-Delay Product\r\n 3.3.5 A Look into the Future: Effects of Technology Scaling\r\n 3.4 The Bipolar ECL Inverter\r\n 3.4.1 Issues in Bipolar Digital Design: A Case Study\r\n 3.4.2 The Emitter-Coupled Logic (ECL) Gate at a Glance\r\n 3.4.3 Robustness and Noise Immunity: The Steady-State Characteristics\r\n 3.4.4 ECL Switching Speed: Thc Transient Behavior\r\n 3.4.5 Power Consumption\r\n 3.4.6 Looking Ahead: Scaling the Technology\r\n 3.5 Perspective: Area, Perfonnance, and Dissipation\r\n 3.6 Summary\r\n 3.7 To Probe Further\r\n 3.8 Exercises and Design Problems\r\nChapter 4: Designing Combinational Logk Cates in CMOS\r\n 4.1 Introduction\r\n 4.2 Static CMOS Design\r\n 4.2.1 Complementary CMOS\r\n 4.2.2 Ratioed Logic\r\n 4.2.3 Pass-Transistor Logic\r\n 4.3 Dynamic CMOS Design\r\n 4.3.1 Dynamic Logic: Basic Principles\r\n 4.3.2 Perfonnance of Dynamic Logic\r\n 4.3.3 Noise Considerations in Dynamic Design\r\n 4.3.4 Cascading Dynamic Gates\r\n 4.4 Power Consumption in CMOS Gates\r\n 4.4.1 Switching Activity of a Logic Gate\r\n 4.4.2 Glitching in Static CMOS Circuits\r\n 4.4.3 Short-Circuit Currents in Static CMOS Circuits\r\n 4.4.4 Analyzing Power Consumption Using SPICE\r\n 4.4.5 Low-Power CMOS Design\r\n 4.5 Perspective: How to Choose a Logic Style\r\n 4.6 Summary\r\n 4.7 To Probe Further\r\n 4.8 Exercises and Design Problems\r\n Appendix C: Layout Techniques for Complex Cates\r\nChapter 5: Very High Perfonnance Digital Circuits\r\n 5.1 Introduction\r\n 5.2 Bipolar Gate Design\r\n 5.2.1 Logic Design in ECL\r\n 5.2.2 Differential ECL\r\n 5.2.3 Current Mode Logic\r\n 5:2.4 ECL with Active Pull-Downs\r\n 5.2.5 Altemative Bipolar Logic Styles\r\n 5.3 The BiCMOS Approach\r\n 5.3.1 The BiCMOS Gate at a Glance\r\n 5.3.2 The Static Behavior and Robustness Issues\r\n 5.3.3 Perfonnance of the BiCMOS Inverter\r\n 5.3.4 Power Consumption\r\n 5.3.5 Technology Scaling\r\n 5.3.6 Designing BiCMOS Digital Gates\r\n 5.4 Digital Gallium Arsenide Design *\r\n 5.4.1 GaAs Devices and Their Properties\r\n 5.4.2 GaAs Digital Circuit Design\r\n 5.5 Low-Temperature Digital Circuits *\r\n 5.5.1 Low-Temperature Silicon Digital Circuits\r\n 5.5.2 Superconducting Logic Circuits\r\n 5.6 Perspective: When to Use High-Performance Technologies\r\n 5.7 Summary\r\n 5.8 To Probe Further\r\n 5.9 Exercises and Design Problems\r\n Appendlx D: The Schottky-Bamer Oiode\r\nChapter 6: Designing Sequential Logic Circuits\r\n 6.1 Introduction\r\n 6.2 Static Sequential Circuits\r\n 6.2.1 Bistability\r\n 6.2.2 Flip-Flop Classification\r\n 6.2.3 Master-Slave and Edge-Triggered FFs\r\n 6.2.4 CMOS Static Flip-Flops\r\n 6.2.5 Bipolar Static Flip-Flops\r\n 6.3 Dynamic Sequentia) Circuits\r\n 6.3.1 The Pseudostatic Latch\r\n 6.3.2 The Dynamic Two-Phase Flip-Flop\r\n 6.3.3 The C2MOS Latch\r\n 6.3.4 NORA-CMOS-A Logic Style for Pipelined Structures\r\n 6.3.5 True Single-Phase Clocked Logic (TSPCL)\r\n 6.4 Non-Bistable Sequential Circuits\r\n 6.4.1 The Schmitt Trigger\r\n 6.4.2 Monostable Sequential Circuits\r\n 6.4.3 Astable Circuits\r\n 6.5 Perspective: Choosing a Clocking Strategy\r\n 6.6 Summary\r\n 6.7 To Probe Funher\r\n 6.8 Exercises and Design Problems\r\n PART 11: A SYSTEMS PERSPECTIVE\r\nChapter 7: Designing Arithmetic Building Blocks\r\n 7.1 Introduction\r\n 7.2 Datapaths in Digital Processor Architectures\r\n 7.3 The Adder\r\n 7.3.1 The Binary Adder: Definitions\r\n 7.3.2 The Full Adder: Circuit Design Considerations\r\n 7.3.3 The Binary Adder: Logic Design Considerations\r\n 7.4 The Multiplier\r\n 7.4.1 The Multiplier: Definitions\r\n 7.4.2 The Array Multiplier\r\n 7.4.3 Other Multiplier Structures\r\n 7.5 The Shifter\r\n 7.5.1 BarrelShifter\r\n 7.5.2 Logarithmic Shifter\r\n 7.6 Other Arithmetic Operators\r\n 7.7 Power Considerations in Datapath Structures\r\n 7.7.1 Reducing the Supply Voltage\r\n 7.7.2 Reducing the Effective Capacitance\r\n 7.8 Perspective: De.sign as aTrade-off\r\n 7.9 Summary\r\n 7.10 To Probe Further\r\n 7.11 Exercises and Design Problems\r\n Appendix E: From Datapath Schematics to Layout\r\nChapter 8: Coping wlth Interconnect\r\n 8.1 Introduction\r\n 8.2 Capacitive Parasitics\r\n 8.2.1 Modeling Interconnect Capacitance\r\n 8.2.2 Capacitance and Reliability-Cross Talk\r\n 8.2.3 Capacitance and Performance in CMOS\r\n 8.2.4 Capacitance and Performance in Bipolar Design\r\n 8.3 Resistive Parasitics\r\n 8.3.1 Modeling and Scaling of Interconnect Resistance\r\n 8.3.2 Resistance and Reliability-Ohmic Voltage Drop\r\n 8.3.3 Electromigration\r\n 8.3.4 Resistance and Performance-RC Delay\r\n 8.4 Inductive Parasitics\r\n 8.4.1 Sources of Parasitic Inductances\r\n 8.4.2 Inductance and Reliability- Voltage Drop\r\n 8.4.3 Inductance and Performance-Transmission Lin5e Effects\r\n 8.5 Comments on Packaging Technology\r\n 8.5.1 Package Materials\r\n 8.5.2 Interconnect Levels\r\n 8.5.3 Thennal Considerations in Packaging\r\n 8.6 Perspective: When to Consider Interconnect Parasitics\r\n 8.7 Chapter Summary\r\n 8.8 To Probe Further\r\n 8.9 Exercises and Design Problems\r\nChapter 9: Timing Issues in Digital Circuits\r\n 9.1 Introduction\r\n 9.2 Clock Skew and Sequential Circuit Performance\r\n 9.2.1 Single-Phase Edge-Triggered Clocking\r\n 9.2.2 Two-Phase Master-Slave Clocking\r\n 9.2.3 Other Clocking Styles\r\n 9.2.4 How to Counter Clock Skew Problems\r\n 9.2.5 Case Study-The Digital Alpha 21164 Microprocessor\r\n 9.3 Self-Timed Circuit Design*\r\n 9.3.1 Selt-Timed Concept\r\n 9.3.2 Completion-Signal Generation\r\n 9.3.3 Self-Timed Signaling\r\n 9.4 Synchronizers and Arbiters*\r\n 9.4.1 Synchronizers-Concept and Implementation\r\n 9.4.2 Arbiters\r\n 9.5 Clock Generation and Synchronization*\r\n 9.5.1 Clock Generators\r\n 9.5.2 Synchronization at the System Level\r\n 9.6 Perspective: Synchronous versus Asynchronous Design\r\n 9.7 Summary\r\n 9.8 To Probe Further\r\n 9.9 Exerci.ses and Design Problems\r\nChapter 10: Designing Memory and Array Structures\r\n 10.1 Introduction\r\n 10.2 Semiconductor Memories--An Introduction\r\n 10.2.1 Memory Classification\r\n 10.2.2 Memory Architectures and Building Blocks\r\n 10.3 The Memory Core\r\n 10.3.1 Read-Only Memories\r\n 10.3.2 Nonvolati le Read-Write Memories\r\n 10.3.3 Read-Write Memories (RAM)\r\n 10.4 Memory Peripheral Circuitry\r\n 10.4.1 The Address Decoders\r\n 10.4.2 Sense Amplifiers\r\n 10.4.3 Drivers/Buffers\r\n 10.4.4 Timing and Control\r\n 10.5 Memory Reliability and Yield\r\n 10.5.1 Signal-To-Noise Ratio\r\n 10.5.2 Memory yield\r\n 10.6 Case Studies in Memory Design\r\n 10.6.1 The Programmable Logic Array (PLA)\r\n 10.6.2 A 4 Mbit SRAM\r\n 10.7 Perspective: Semiconductor Memory Trends and Evolutions\r\n 10.8 Summary\r\n 10.9 To Probe Further\r\n 10.10 Exercises and Design Problems\r\nChapterll: Deslgn Methodologles\r\n 11.1 Introduction\r\n 11.2 Design Analysis and Simulation\r\n 11.2.1 Representing Digital Data as a Continuous Entity\r\n 11.2.2 Representing Data as a Discrete Entity\r\n 11.2.3 Using Higher-Level Data Models\r\n 11.3 Design Verification\r\n 11.3.1 Electrical Verification\r\n 11.3.2 Timing Verification\r\n 11.3.3 Functional (or Fonnal) Verification\r\n 11.4 Implementation Approaches\r\n 11.4.1 Custom Circuit Design\r\n 11.4.2 Cell-Based Design Methodology\r\n 11.4.3 Anay-Based Implementation Approaches\r\n 11.5 Design Synthesis\r\n 11.5.1 Circuit Synthesis\r\n 11.5.2 Logic Synthesis\r\n 11.5.3 Architecture Synthesis\r\n 11.6 Validation and Testing of Manufactured Circuits\r\n 11.6.1 TestProcedure\r\n 11.6.2 Design for Testability\r\n 11.6.3 Test-Pattem Generation\r\n 11.7 Perspective and Summary\r\n 11.8 To Probe Further\r\n 11.9 Exercises and Design Problems\r\nProblem Solutions\r\n

从事数字集成电路设计的人对于Jan M.Rabaey所著的Digital Integrated Circuits：A Design Perspective(《数字集成电路——设计透视》)一书应该不陌生。该书第1版于1996年由Pearson Education公司出版， 1998年清华大学出版社出版了该书的英文影印版，并多次增印，成为国内集成电路设计人员以及相关专业学生手中经典的参考书。时隔7年后的2003年，Jan M.Rabaey,Anantha Chandrakasan以及Borivoje Nikolic三人终于合著出版了该书的第2版。 在这7年中，CMOS制造技术依然保持着快速的发展步伐，最小线宽已经进入100nm以内，电路变得越来越复杂，超深亚微米的制造工艺使得器件的行为变得更加复杂；由此带来了数字集成电路可靠性、成本、性能、功耗等多方面的新问题，对电路设计者提出了新的挑战。因此本书作者们在第2版中特别关注了深亚微米效应、互连线、信号完整性、高性能与低功耗设计、时序优化与时钟分布等问题，并通过最新的设计实例介绍了这些方面的进展。另外超过99％的数字集成电路产品采用了MOS技术，因此第2版删除了双极电路和砷化镓器件的内容。针对设计方法学在当今设计流程中的重要性，在第2版中还加入了若干“设计方法学”章节(design methodology insert)，专门介绍设计流程中的某个具体的方面。 全书共分为12章，3个部分。其中第一部分为第1章至第4章，分别介绍了MOS制造过程、半导体器件模型以及在深亚微米设计中非常重要的互连线。第二部分为第5章至第7章，这部分从电路的角度分析了数字集成电路，包括全书最重要也是最基础的反相器分析以及其他门电路的知识，第7章还给出了时序电路的基本概念。第三部分为第8章至第12章，从系统的角度分析了数字集成电路设计，包括互连线在深业微米条件下对系统功能和性能的影响、时序约束和时钟分布问题等。 本书的特点主要包括： (1)将数字集成电路设计中电路与系统的视角统一起来，在系统深入地介绍了深亚微米条件下半导体器件的知识和最基本的反相器后，作者逐渐将这些基础知识引入到更加复杂的模块，比如门、寄存器、控制器、加法器、乘法器和存储器等。在深亚微米的设计条件下，设计者不仅仅需要考虑整个系统的设计问题，还要随时警惕在电路级——比如器件和连线所带来的问题。 (2)本书是第一本将数字集成电路设计问题集中在深亚微米条件下的参考书，并且提供了一个深亚微米条件下的简单晶体管模型。另外针对深亚微米条件下设计人员所面对的新挑战，例如互连线问题、信号完整性问题、时钟分布问题、功耗问题等，全书都做了非常详细的论述。 (3)书中的内容紧扣当今数字集成电路设计的核心问题，并通过大量的设计实例向读者介绍了最新的设计技术和工程发展现状与趋势。 (4)与本书相配套的互联网站点http://bwrc.eecs.berkeley.edu/IcBook/index.htm，为读者提供了大量的习题和其他实验资料。 全书结构清晰，语言流畅。在讨论深奥的理论问题时，娓娓道来，深入浅出，非常适合作为教材或者自学者使用。相信读者通过阅读参考此书，一定会受益匪浅。

微电子技术是信息科学技术的核心技术之一，微电子产业是当代高新技术产业群的核心和维护国家主权、保障国家安全的战略性产业。我国在《信息产业“十五”计划纲要》中明确提出：坚持自主发展，增强创新能力和核心竞争力，掌握以集成电路和软件技术为重点的信息产业的核心技术，提高具有自主知识产权产品的比重。发展集成电路技术的关键之一是培养具有国际竞争力的专业人才。 微电子技术发展迅速，内容更新快，而我国微电子专业图书数量少，且内容和体系不能反映科技发展的水平，不能满足培养人才的需求，为此，我们系统挑选了一批国外经典教材和前沿著作，组织分批出版。图书选择的几个基本原则是：在本领域内广泛采用，有很大影响力；内容反映科技的最新发展，所述内容是本领域的研究热点；编写和体系与国内现有图书差别较大，能对我国微电子教育改革有所启示。本套丛书还侧重于微电子技术的实用性，选取了一批集成电路设计方面的工程技术用书，使读者能方便地应用于实践。本套丛书不仅能作为相关课程的教科书和教学参考书，也可作为工程技术人员的自学读物。 我们真诚地希望，这套丛书能对国内高校师生、工程技术人员以及科研人员的学习和工作有所帮助，对推动我国集成电路的发展有所促进。也衷心期望着广大读者对我们一如既往的关怀和支持，鼓励我们出版更多、更好的图书。