The third edition of Computer Architecture: A Quantitative Approach should have been easy to write. After all, our quantitative approach hasn't changed, and we sought to continue our focus on the basic principles of computer design through two editions. The examples had to be updated, of course, just as we did for the second edition. The dramatic and ongoing advances in the field as well as the creation of new markets for computers and new approaches for those markets, however, led us to rewrite almost the entire book.
The pace of innovation in computer architecture continued unabated in the six years since the second edition. As when we wrote the second edition, we found that numerous new concepts needed to be introduced, and other material designated as more basic. Although this is officially the third edition of Computer Architecture: A Quantitative Approach, it is really our fifth book in a series that began with the first edition, continued with Computer Organization and Design:The Hardware/Software Interface (COD:HSI), and then the second edition of both books. Over time ideas that were once found here have moved to COD:HSI or to background tutorials in the appendices. This migration, combined with our goal to present concepts in the context of the most recent computers, meant there was remarkably little from the second edition that could be preserved intact, and practically nothing is left from the first edition.
Chapter 1 Fundamentals of Computer Design
1.1 Introduction
1.2 The Changing Face of Computing and the Task of the Computer Designer
1.3 Technology Trends
1.4 Cost, Price, and Their Trends
1.5 Measuring and Reporting Performance
1.6 Quantitative Principles of Computer Design
1.7 Putting It All Together: Performance and Price-Performance
1.8 Another View: Power Consumption and Efficiency as the Matric
1.9 Fallacies and Pitfalls
1.10 Concluding Remarks
1.11 Historical Perspective and References
Exercises
Chapter 2 InStruction Set Prindples and Examples
2.1 Introduction
2.2 Classifying Instruction Set Architectures
2.3 Memory Addressing
2.4 Addressing Modes for Signal Processing
2.5 Type and Size of Operands
2.6 Operands for Media and Signal Processing
2.7 Operations in the Instruction Set
2.8 Operations for Media and Signal Processing
2.9 Instructions for Control Flow
2.10 Encoding an Instruction Set
2.11 Crosscutting lssues:The Role of Compilers
2.12 Putting It All Together:The MIPS Architecture
2.1 3 Another View: The Trimedia TM32 CPU
2.14 Fallacies and Pitfalls
2.15 Concluding Remarks
2.16 Historical Perspective and References
Exercises
Chapter 3 Instruction-Level Parallelism and Its Dynamic Exploitation
3.1 Instruction-Level Parallelism:Concepts and Challenges
3.2 Overcoming Data Hazards with Dynamic Scheduling
3.3 Dynamic Scheduling: Examples and the Algorithm
3.4 Reducing Branch Costs with Dynamic Hardware Prediction
3.5 High-Performance Instruction Delivery
3.6 Taking Advantage of More ILP with Multiple Issue
3.7 Hardware-Based Speculation
3.8 Studies of the Limitations of ILP
3.9 Limitations on ILP for Realizable Processors
3.10 Putting It All Together: The P6 Microarchitecture
3.11 Another View: Thread-Level Parallelism
3.12 Crosscutting lssues: Using an ILP Data Path to Exploit TLP
3.13 Fallacies and Pitfalls
3.14 Concluding Remarks
3.15 Historical Perspective and References
Exercises
Chapter 4 Exploiting Instruction-Level Parallelism with Software Approaches
4.1 Basic Compiler Techniques for Exposing ILP
4.2 Static Branch Prediction
4.3 Static Multiple Issue: The VLIW Approach
4.4 Advanced Compiler Support for Exposing and Exploiting ILP
4.5 Hardware Support for Exposing More Parallelism at Compile Time
4.6 Crosscutting Issues: Hardware versus Software
Speculation Mechanisms
4.7 Putting It All Together:The Intel IA-64 Architecture and Itanium Processor
4.8 AnotherView: ILP in the Embedded and Mobile Markets
4.9 Fallacies and Pitfalls
4.10 Concluding Remarks
4.11 Historical Perspective and References
Exercises
Chapter 5 Memory Hierarchy Design
5.1 Introduction
5.2 Review of the ABCs of Caches
5.3 Cache Performance
5.4 Reducing Cache Miss Penalty
5.5 Reducing Miss Rate
5.6 Reducing Cache Miss Penalty or Miss Rate via Parallelism
5.7 Reducing Hit Time
5.8 Main Memory and Organizations for Improving Performance
5.9 Memory Technology
5.10 Virtual Memory
5.11 Protection and Examples of Virtual Memory
5.12 Crosscutting Issues: The Design of Memory Hierarchies
5.13 Putting It All Together: Alpha 21264 Memory Hierarchy
5.14 Another View: The Emotion Engine of the Sony Playstation 2
5.15 Another View: The Sun Fire 6800 Server
5.16 Fallacies and Pitfalls
5.17 Concluding Remarks
5.18 Historical Perspective and References
Exercises
Chapter 6 Multiprocessors and Thread-Level Parallelism
6.1 Introduction
6.2 Characteristics of Application Domains
6.3 Symmetric Shared-Memory Architectures
6.4 Performance of Symmetric Shared-Memory Multiprocessors
6.5 Distributed Shared-Memory Architectures
6.6 Performance of Distributed Shared-Memory Multiprocessors
6.7 Synchronization
6.8 Models of Memory Consistency: An Introduction
6.9 Multithreading: Exploiting Thread-Level Parallelism within a Processor
6.10 Crosscutting Issues
6.11 Putting It All Together: Sun's Wildfire Prototype
6.12 Another View Multithreading in a Commercial Server
6.13 Another View f Embedded Multiprocessors
6.14 Fallacies and Pitfalls
6.15 Concluding Remarks
6.16 Historical Perspective and References
Exercises
Chapter 7 Storage Systems
7.1 Introduction
7.2 Types of Storage Devices
7.3 Buses--Connecting I/O Devices to CPU/Memory
7.4 Reliability, Avai1ability, and Dependability
7.5 RAlD: Redundant Arrays of Inexpensive Disks
7.6 Errors and Failures in Real Systems
7.7 I/O Performance Measures
7.8 A Little Queuing Theory
7.9 Benchmarks of Storage Performance and Availability
7.10 Crosscutting Issues
7.11 Designing an I/O System in Five Easy Pieces
7.12 Putting It All Together: EMC Symmetrix and Celerra
7.13 Another View: Sanyo VPC-SX500 Digital Camera
7.14 Fallacies and Pitfalls
7.15 Concluding Remarks
7.16 Historical Perspective and References
Exercises
Chapter 8 Interconnection Networks and Clusters
8.1 Introduction
8.2 A Simple Network
8.3 Interconnection Network Media
8.4 Connecting More Than Two Computers
8.5 Network Topology
8.6 Practical Issues for Commercial Interconnection Networks
8.7 Examp1es of Interconnection Networks
8.8 Internetworking
8.9 Crosscutting Issues for Interconnection Networks
8.10 Clusters
8.11 Designing a C1uster
8.12 Putting It All Together: The Google Cluster of PCs
8.13 Another View: Inside a Cell Phone
8.14 Fallacies and Pitfalls
8.15 Concluding Remarks
8.16 Historical Perspective and References
Exercises
Appendix A Pipelining: Basic and Intermediate Concepts
A.1 Introduction
A.2 The Major Hurdle of Pipelining--Pipeline Hazards
A.3 How Is Pipelining Implemented?
A.4 What Makes Pipelining Hard to Implement?
A.5 Extending the MIPS Pipeline to Handle Multicycle Operations
A.6 Putting It All Together: The MIPS R4000 Pipeline
A.7 Another View: The MIPS R4300 Pipeline
A.8 Crosscutting Issues
A.9 Fallacies and Pitfalls
A.10 Concluding Remarks
A.11 Historical Perspective and References
Exercises
Appendix B Solutions to Selected Exercises
Introduction
B.1 Chapter 1 Solutions
B.2 Chapter 2 Solutions
B.3 Chapter 3 Solutions
B.4 Chapter 4 Solutions
B.5 Chapter 5 Solutions
B.6 Chapter 6 Solutions
B.7 Chapter 7 Solutions
B.8 Chapter 8 Solutions
B.9 Appendix A Solutions
Online Appendices (www.mkp.com/CA3/)
Appendix C A Survey of RISC Architectures for Desktop, Server,and Embedded Computers
Appendix D An Alternative to RISC:The Intel 80X86
Appendix E Another Alternative to RISC:The VAX Architecture
Appendix F The IBM 360/370 Architecture for Mainframe Computer
Appendix G Vector Processors
Revised by Krste Asanovic
Appendix H Computer Arithmotic
by David Goldberg
Appendix I Implementing Coherence Protocols
References
Index
Why We Wrote This Book
Through three editions of this book, our goal has been to describe the basic principles underlying what will be tomormw's technological developments. Our excitement about the Opportunities in computer architecture has not abated, and we echo what we said about the field in the first edition: "It is not a dreary science of paper machines that will never work. No! It's a discipline of keen intellectual interest, requiring the balance of marketplace forces to cost-performance-power,leading to glorious failures and some notable successes."
Our primary objective in writing our first book was to change the way people learn and think about computer architecture. We feel this goal is still valid and important. The field is changing daily and must be studied with real examples and measurements on real computers, rather than simply as a collection of definitions and designs that will never need to be realized. We offer an enthusiastic welcome to anyone who came along with us in the past, as well as to those who are joining us now Either way, we can promise the same quantitative apprach to, and analysis of, real systems.
As with earlier versions, we have strived to produce a new edition that will continue to be as relevant for professional engineers and architects as it is for those involved in advanced computer architecture and design courses. As much as its predecessors, this edition aims to demystify computer architecture through an emphasis on cost-pdriance-power trade-offs and good engineering design.We believe that the field has continued to mature and move toward the rigorous quantitative foundation of long-established scientific and engineering disciplines. Our greatest satisfaction derives from the fact that the principles described in our first edition in l990 and the second edition in l996 could be applied successfully to help predict the landscape of computing technology that exists today. We hope that this third edition will allow reader to apply the fundamentals for similar results as we look forward to the coming decades.
This Edition
The third edition of Computer Architecture: A Quantitative Approach should have been easy to write. After all, our quantitative approach hasn't changed, and we sought to continue our focus on the basic principles of computer design through two editions. The examples had to be updated, of course, just as we did for the second edition. The dramatic and ongoing advances in the field as well as the creation of new markets for computers and new approaches for those markets, however, led us to rewrite almost the entire book.
The pace of innovation in computer architecture continued unabated in the six years since the second edition. As when we wrote the second edition, we found that numerous new concepts needed to be introduced, and other material designated as more basic. Although this is officially the third edition of Computer Architecture: A Quantitative Approach, it is really our fifth book in a series that began with the first edition, continued with Computer Organization and Design:The Hardware/Software Interface (COD:HSI), and then the second edition of both books. Over time ideas that were once found here have moved to COD:HSI or to background tutorials in the appendices. This migration, combined with our goal to present concepts in the context of the most recent computers, meant there was remarkably little from the second edition that could be preserved intact, and practically nothing is left from the first edition.
Perhaps the biggest surprise for us was the realization that the computer architecture field had split into three related but different market segments, each with their own needs and somewhat different architectures to address them. The cost Performance theme of our first and second editions is currently best exemplified by desktop computers. The two new paths are embedded computers and server computers. This major shift in the field is reflected in this edition by two major changes. First, throughout the text we broaden the topics considered as well as the metrics of success. Second, a new section, called "Another View," supplements the more traditional examples in "Putting It All Together" with examples that include video games, digital cameras, and cell phones.
Embedded computers have much lower cost targets than do desktop computers. They are often employed in environments where they run a single application. Also, embedded computers often rely on batteries and cannot use active cooling mechanisms, and energy/Power efficiency is thus critical. To illustrate the design trade-offs and approaches in embedded processors we made several additions: the EEMBC benchmarks are used to evaluate performance, media Processor and DSP instruction set principles and measurements are examined, the most popular embedded instruction set architectures are surveyed in the appendices, and performance-power trade-offs are explored in several chapters. Power sensitive examples inc1ude the Transmeta and low-power MIPS Processors, and embedded systems examples include the PlayStation-2 video game, Sanyo digital camera, and Nokia cell phone.
Server computers place more emphasis on reliability, scalability, and on throughput rather than latency to measure Performance. Thus, these systems typically include multiple processors and disks. This edition explains the concept of dependability and includes rarely found statistics on the frequency of component failures. In addition to the SPEC2000 benchmarks for processors, we examine the TPC database benchmarks and the SPEC benchmars for file servers. Exarnples of server processors include the Intel IA-64 and the Sun UltraSPARC III, and exarnples of server systems include the Sun Fire 6800, the Sun Wildfire, EMC Symmetrix, EMC Celerra, the Google cluster, and an IBM cluster for transaction processing.
This edition continues the tradition of using real-world examples to demonstrate the ideas, and the "Putting It All Together" sections are essentially l00% new. The "Putting It All Together" sections of this book include the MIPS64 instruction set architecture, the Intel Pentium In and 4 pipeline organization, the Intel IA-64 architecture and microarchitecture, the Alpha 2l264 memory hierarchy, the Sun Wildfire multiprocessor, the EMC Symmetrix storage array, the EMC Celerra file server, and the Google search engine. The "Another View" sections pick real-worid examples from the embedded and server communities. This list has the Trimedia TMS media processor, a PowerPC multithreaded processor,the memory hierarchy of Emotion Engine in the Sony Playstation-2, Sun Fire 6800/UltraSPARC III memory hierarchy, EmpowerTel MXP embedded multiprocessor, Sanyo digital camera, and Nokia cell phone.In response to numerous comments, considerable effort was focused on revising and enhancing the exercises. In particular all the exercises were reviewed to try to reduce ambiguities and eliminate unproductive exercises, and many new exercises were developed. As many readers requested, Appendix B provides answers to selected exercises.
We also added some new features that should help readers. We replaced the synthetic 32-bit DLX architecture with the popular 64-bit MIPS architecture, as it just made more sense to use existing software rather than recreate and maintain compilers ourselves. We also added a large set of appendices that contains descriptions of a dozen instruction set architectures plus tutorials on basic pipelining, vector processors, and floating-point arithmetic.
Topic Selection and Organization
As before, we have taken a conservative approach to topic selection, for there are many more interesting ideas in the field than can reasonably be covered in a treatment of basic principles. We have steered away from a comprehensive survey of every architecture a reader might encounter.Instead, our presentation focuses on core concepts likely to be found in any new machine. The key criterion remains that of selecting ideas that have been examined and utilized successfully enough to permit their discussion in quantitative terms.
Our first dilemma in determining the new topic selections was that topics requiring only a few pages in the prior editions have since exploded in their importance. Second, topics that we excluded previously have matured to a point where they can be discussed based on our quantitative criteria and their success in the marketplace. To allow for this new material, we reduced the extent of introductory material, assuming the knowledge of the concepts in our introductory text Computer Organization and Design: The Hardware/Software Interface.Appendix A on pipelining was added as a valuable tutorial for readers not familiar with the basics of pthelining. (Readers interested strictly in a more basic introduction to computer architecture should read Computer Organization and Design: The Hardware/Software Interface.)
Our intent has always been to focus on material that is not available in equivalent form from othe sources, so we contine to emphasize advanced content wherever possible. Indeed, there are several systems here whose descriptions cannot be found in the literature.
An Overview of the Content
Chapter l covers the basic quantitative principles of computer design and performance measurement. It also addresses the role of technology and the factors affecting the cost of computer systems. It concludes by examining Performance and price-performance measurements of processors designed for the desktop,server, and embedded markets, as well as considering the power efficiency Of embedded processors.
Chapter 2 covers instruction set design principles and examples. In addition to giving quantitative data on instruction set usage based on the SPEC2000 benchmarks, it describes the MIPS64 architecture used throghout the book. New to this edition are principles of digital signal processor architectures, including common features and measurements. It describes the Structure of modern compilers and how that affects the utility of instruction sets for traditional computers, DSPs,and media extensions. It also gives the Trimedia TM5200 as a contrasting example of a media processor, offering instruction mixes for both it and MIPS. Appendices C to G extend this chapter by describing a dozen other popular instruction sets.
Chapters 3 and 4 cover the exploitation of instructinn-level parallelism in high-performance processors, including superscalar execution, branch prediction,speculation, dynamic scheduling, and the relevant compiler technology. These topics have grown so much that, even with the creation of a l00-page appendix based on Chapter 3 of the second edition, we still needed two chapters to cover the advanced material. Chapter 3 of this edition focuses on hardware-based approaches to exploiting instruction-level parallelism, while Chapter 4 focuses on more static approaches that rely on more sophisticated compiler technology. The Intel Pentium series is used as the major example in Chapter 3, while Chapter 4 examines the IA-64 architecture and its first implementation in Itanium.
Chapter 5 starts with an introductory review of cache principles. It then reorganizes the optimizations in memory hierarchy design to what are the major challenges today. In addition to real-world examples from traditional computers such as the Alpha 2l264, AMD Athlon, and Intel Pentium III and 4, it describes the memory hierarchy of the Emotion Engine in the Sony Playstation-2 video game and the Sun Fire 6800 server with its UltraSPARC III processoL This edition describes the techniques of the bandwidth-optimized DRAM chips such as RAMBUS, and comments on their cost-Performance. It also includes cache performance of multimedia and server applications in addition to the SPEC2000 benchmarks for the desktop.
Chapter 6 discusses multiprocessor systems, focusing on shared-memory architectures. The chapter begins by examining the properties of different application domains with thread-level parallelism. It then explores symmetric and distributed memory architectures, examining both organizational principles and Performance. Topics in synchronization, memory consistency models, and multithreading (including simultaneous multithreading) complete the foundational chapters. Sun's Wi1dfire design, which uses a distributed memory architecture to extend the reach of a symmetric approach, is discussed and analyzed.
Chapter 7, "Storage Systems,: saw a surprising amount of revision. There is an expansion of reliability and availability, a tutorial on RAID, availability benchmarks, and rarely found failure statistics of real systems. It continues to provide an introduction to queuing theory and I/O Performance benchmarks. It extends the description of traditional buses with embedded and server buses. The five design examples in later sections evolve an I/O system through increasingly realistic Performance assumptions, plus an evaluation of the mean time to failure. EMC supplies the examples that put it all together, which is the first time these systems have been documented publicly. The anatomy of a digital camera offers an embedded perspective on storage systems, and the historical perspective includes a ringside view of the development and popularity of RAID.
A goal of Chapter 8 is to provide an introduction to networks from the computer architecture point of view. Since this field is vast and quickly moving, the emphasis here is on an introduction to the terminology and principles. It starts with providing a common framework for the design principles in local area networks, storage area networks, and wide area networks, concluding with a description of the technology of the Internet. The second part of Chapter 8 is an in-depth exploration of clusters and the pros and cons of the use of clusters in both scientific computing and database applications. There is a detailed evaluation of the cost-performance of clusters, including the cost of machine room space and network bandwidth. The first description of the cluster used to provide the popular Google search engine puts this chapter together.
This brings us to Appendices A through I. Appendix A is a tutorial on basic pipelining concepts. Readers relatively new to pipelining should read this appendix before Chapters 3 and 4. As mentioned earlier, Appendix B contains solutions to selected exercises. Given the ubiquity of the Web today, the remaning appendices are online, which allows us to add relevant information without increasing the weight or cost of the book. Appendix C updates the second edition RISC appendix, describing 64-bit versions of Alpha, MIPS, PowerPC, and SPARC and their multimedia extensions. Also included in this appendix are popular embedded instruction sets: ARM, Thumb, SuperH, MIPSl6, and Mitsubishi M32R.Appendix D describes the 80x86 architecture. Since we have no page budget for the online appendices, we include two architectures of more historical interest: the VAX (Appendix E) and IBM 360370 (Appendix F). Appendix G includes an updated description of vector processors. Finally, Appendix H describes computer arithmetic, and Appendix I describes implementing coherence protocols.
In summary, about 70% of the pages are new to this edition. The third edition is also about l0% longer than the first if we don't include the online appendices, and about 30% longer if we do.
第二书店&China-pub战略联盟提供专业服务
第二书店联系方式 010-64348411 webmaster@dearbook.com